1. Field of the Invention
The present invention relates to a phase-locked loop (PLL) controller for controlling a phase-locked loop provided for, e.g. a digital video decoder for decoding video signals, and, in particular, a PLL controller for controlling a coefficient to be input to a device such as an analog multiplier in the phase-locked loop. The present invention also relates to a method for controlling the same.
2. Description of the Background Art
Conventionally, in devices such as digital video decoders, a frequency error has occurred between an input video signals and the reference signal, thus providing a jittered video image.
For example, as shown in FIG. 5, a video signal 400 generally has sets of vertical blanking period 402 and effective video period 404. In each of the sets, the period of a field is defined starting with a vertical sync pulse 406 in the vertical blanking period 402. Furthermore, as shown in FIG. 6 depicting a part 408 in the effective video period 404 of the video signal 400 enlarged, each horizontal line has sets of horizontal blanking period 412 and effective video period 414. In each of the sets, the period of a line is defined starting with a horizontal sync pulse 416 in the horizontal blanking period 412.
Some type of digital video decoders contains a phase-locked loop to generate a line lock clock signal locked to the period of one line. The line lock clock signal is used to sample an analog video signal so as to allow the same part of each line to be sampled to thereby obtain jitter-free video images.
However, some kinds of video signals are not standardized but include a line whose period is deviated from the standardized period, i.e. not consistent with the reference period. For example, if a video signal is reproduced by a video cassette player (in a normal or special reproduction), each line may have its actual period contain a little error against the reference period, so that the signal may include a line of which the error is larger. In a television broadcast system, transmitting video signals on weak electric field waves, even though video signals consisting of the lines consistent with the reference period are transmitted, they will be received with noise mixed so that the period of each line will be falsely detected.
Correspondingly, some kind of conventional PLL controllers for controlling a phase-lock loop is adapted to change, in the case of a video signal reproduced by a video cassette player or from a weak electric field signal of television, the tracking rate of the phase-locked loop in response to an external command. When such controllers process a signal reproduced by a video cassette player, the controllers have the phase-locked loop quickly, or strongly, track the errors in the lines of the signal to attain video images with less jitter. When the controllers process a weak electric field signal of television, the controllers have the phase-locked loop slowly, or weakly, track the errors in the lines of the signal to curb the influence from the false detection of the period of each line as much as possible.
For example, as shown in FIG. 7, a phase-locked loop 20 receives a horizontal sync signal 112 obtained from a video signal by sync separation, compares the horizontal sync signal 112 with a reference signal 130 having a reference period by a phase comparator 22 to determine a phase error 114, and filters the phase error 114 with a filter 24 to obtain a process result 116. Furthermore, the phase-locked loop 20 multiplies the process result 116 by a certain coefficient 434 by multipliers 26 and 28 to obtain multiplied results 118 and 120, respectively, and stores the multiplied result 120 in a delay circuit 30 to obtain a delay result 122. The phase-locked loop 20 further forms a control signal 126 by a voltage-controlled oscillator (vco) 32 according to the multiplied result 118 and the delay result 122 to output to an analog phase-locked loop 34, and forms a reference signal 130 by a line counter 36 in response to a line lock clock signal 128 from the analog phase-locked loop 34.
In a conventional PLL controller 420, provided in connection with the phase-locked loop 20, a control signal 432 is input from outside, which indicates whether a video signal is one reproduced by a video cassette player or a weak electric field signal of television. In response to the input control signal 432, a coefficient switch 422 selects a coefficient 434 to be output to the multipliers 26 and 28 so as to appropriately control the tracking rate of the phase-locked loop 20.
Japanese laid-open publication No. 224732/1998 discloses a determining circuit for determining a special reproduction signal which circuit has a counter for counting clocks of a signal reproduced by a video cassette player. The leading edge of a vertical sync signal is detected by an edge detector. The counter is cleared at the timing of the leading edge thus detected, and counts the number of clocks in each period. The number of clocks in one period is compared with the number of reference clocks by a comparator, thus enabling it to determine whether the reproduced signal is of a fast forwarding replay or rewinding replay.
Japanese laid-open publication No. 2003-23597 discloses a video processor which has a sync processor using a phase-locked loop for synchronizing vertical, interlace, horizontal and chroma signals to measure a pullout in the phase-locked loop; and a determining means for using the measurement signal of a pullout in the phase-locked loop obtained by the sync processor to determine the parameters of the weak electric field. When a certain number of pullouts occur at a predetermined period of time, the video processor cancels the detection result of a copy guard signal.
However, in the conventional PLL controllers, a coefficient input to a multiplier in a phase-locked loop has to be controlled from outside, and therefore types of a video signal to be input to the phase-locked loop should be recognized in advance.